The design of output drivers in integrated circuitry is often a compromise between speed, power consumption and current drive capability. Improvements in one of these areas often cause degradation in another. For example, an increase in drive current causes slower operation of the driver due to the longer discharge time necessary to pull the current from the base of a bipolar transistor or the charge from the gate of a field effect transistor. In addition, the increased current often must pass through internal resistors which increase power consumption of the integrated circuit. For example, FIG. 1 is a schematic diagram of a standard emitter coupled logic (ECL) output driver. The input signal is applied to the base of transistor 1 which is differentially coupled to transistor 2. The base of transistor 2 is tied to a threshold voltage which is equal to the median between the logical high voltage and logical low voltage of the digital circuit. The logical high voltage is generally on the order of -0.8 volts and the logical low voltage level is generally on the order of -1.3 volts in typical ECL circuitry. Transistor 4 and resistor 5 provide a current source for differential transistors 1 and 2. When the input signal to the base of transistor 1 is higher than V.sub.T, the current provided by transistor 4 and resistor 5 flows through transistor 1 and the voltage drop across resistor 3 is the base current of transistor 6 multiplied by the resistance of resistor 3. This pulls the base of transistor 6 high to provide a logical high output signal across resistor 7 and capacitor 8, which are connected via output pin 9 to output buffer 10. A small amount of current through the base of transistor 6 will cause a small voltage drop across resistor 3. When a logical low is provided at the base of transistor 1, transistor 1 turns off and the current provided by transistor 4 and resistor 5 flows through transistor 2 and resistor 3. This current causes a voltage drop across resistor 3. Output pin 9 is then pulled to a low output voltage.
Output driver 10 is limited in its operation by the need to provide the drive current for transistor 6 through resistor 3. Resistor 7 and capacitor 8 are standard pull down devices for ECL circuitry. Assuming a pull down voltage of -2.2 volts, a logical high voltage on output pin 9 must be at least -1 volt to meet minimum logic definition standards. Thus a voltage drop of 1.2 volts is available across resistor 7. To provide maximum drive current and thus maximum speed, output drive current must be maximized. The maximum drive current through resistor 7, which has a value of 25 ohms, is 1.2 volts divided by 25 ohms or 48 milliamperes. Assuming a typical beta (B.sub.F) of 50 at 0 degrees Centigrade for transistor 6, the base current of transistor 6 equals: ##EQU1## where I.sub.E6 is the emitter current of transistor 6, and I.sub.B6 is the base current of transistor 6.
I.sub.B6 passes through resistor 3 which cause a voltage drop V.sub.R3. Summing the voltages from ground to output pin 9 yields the equation: EQU O (ground, assuming no bus drop)-where V.sub.BE6 is the base to emitter drop of transistor 6 and -1.0 is the voltage at output pin 9.
Solving for V.sub.R3 =1 -0.860=140 mV. The R.sub.3 maximum R.sub.3 is thus V.sub.R3 /I.sub.B6 =140 mV/941 .mu.A=148.7 ohms.
A typical voltage swing at the collector of transistor 2 is approximately 930 millivolts. This gives a minimum collector current of 930 millivolts divided by 148.7 ohms or 6.25 milliamps. For a large array of more than 100 outputs, this switching current would cause a power of 6.25 milliamps.times.5.7 volts.times.100 gates which is equal to approximately 3.56 watts of power dissipation. This is a great deal of power to be dissipated on a single integrated circuit and necessitates expensive cooling measures such as air flow fins, forced air cooling, and water jacket cooling.